View IDT8T49N004I_8524166.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

idt8t49n004anlgi revision a october 15, 2013 1 ?2013 integrated device technology, inc. datasheet IDT8T49N004I programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs general description the IDT8T49N004I is a four output clock generator with selectable lvds or lvpecl outputs. the IDT8T49N004I can generate any one of four frequencies from a single crystal or reference clock. the four frequencies are selected from the frequency selection table (table 3a) and are programmed via i 2 c interface. the four predefined frequencies are selected in the user application by two frequency selection pins. note the desired programmed frequencies must be used with the corresponding crystal or clock frequency as indicated in table 3a. excellent phase noise performance is maintained with idt?s fourth generation femtoclock ? ng pll technology, which delivers sub-400fs rms phase jitter. features ? fourth generation femtoclock ng pll technology ? four selectable lvpecl or lvds outputs via i 2 c ? clk, nclk input pair can accept the following differential input levels: lvpecl, lvds, hcsl ? femtoclock ng vco range: 1.91ghz - 2.5ghz ? rms phase jitter at 156.25mhz (12khz - 20mhz): 228fs (typical) ? rms phase jitter at 156.25mhz (10khz - 1mhz): 175fs (typical) ? full 2.5v or 3.3v power supply ? i 2 c programming interface ? pci express (2.5gb/s), gen 2 (5gb/s), and gen 3 (8gb/s) jitter compliant ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging pin assignment IDT8T49N004I 32-lead vfqfn 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm e-pad nl package v ee q0 nq0 v cco q1 nq1 v ee nc fsel1 v ee q2 nq2 v cco q3 nq3 v ee 12345678 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 xtal_in v cc v ee fsel0 nclk clk v ee xtal_out sclk s data v ee v cca lock v ee v cc clk_sel
idt8t49n004anlgi revision a october 15, 2013 2 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs block diagram
idt8t49n004anlgi revision a october 15, 2013 3 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 7, 11, 15, 18, 24, 27, 30 v ee power negative supply pins. 2, 3 q0, nq0 output differential output pair. lvpecl or lvds interface levels. 4, 21 v cco power output supply pins. 5, 6 q1, nq1 output differential output pair. lvpecl or lvds interface levels. 8 nc unused no connect. 9, 10 xtal_in xtal_out input crystal oscillator interface. xtal_in is the input, xtal_out is the output. crystal frequency is selected from table 3a. 12 clk input pulldown non-inverting differential clock input. 13 nclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v cc /2. 14, 17 fsel0, fsel1 input pulldown frequency and configuration. selects between one of four factory programmable power-up default configurations. the four configurations can have different pll states, output frequencies, output styles and output states. these default configurations can be overwritten after power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 = configuration 3 16, 31 v cc power core supply pins. 19, 20 nq3, q3 output differential output pair. lvpecl or lvds interface levels. 22, 23 nq2, q2 output differential output pair. lvpecl or lvds interface levels. 25 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 26 sdata i/o pullup i 2 c data input. input: lvcmos/lvttl interface levels. output: open drain. 28 v cca power analog supply pin. 29 lock output pll lock indicator. lvcmos/lvttl interface levels. 32 clk_sel input pulldown input source control pin. lvcmos/lvttl interface levels. 0 = xtal (default) 1 = clk, nclk symbol parameter test conditions minimum typical maximum units c in input capacitance 3.5 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
idt8t49n004anlgi revision a october 15, 2013 4 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs frequency configuration table 3a. frequency configuration examples output frequencies (mhz) input frequency or crystal frequency (mhz) input clock divider p input clock prescaler ps feedback divider m output divider n vco frequency (mhz) 30.72 30.72 1 x2 32 64 1966.08 61.44 30.72 1 x2 32 32 1966.08 62.5 25 1 x2 40 32 2000 76.8 30.72 1 x2 40 32 2457.6 78.125 25 1 x2 50 32 2500 100 25 1 x2 40 20 2000 106.25 26.5625 1 x2 40 20 2125 122.8 30.72 1 x2 32 16 1966.08 125 25 1 x2 40 16 2000 133.33 25 1 x2 48 18 2400 148.5 27 1 x2 44 16 2376 150 25 1 x2 42 14 2100 153.6 30.72 1 x2 40 16 2457.6 155.52 19.44 1 x2 64 16 2488.32 156.25 25 1 x2 50 16 2500 100 2 x1 50 16 2500 125 5 x2 50 16 2500 159.375 26.5625 1 x2 36 12 1912.5 160 20 1 x2 48 12 1920 166.66 25 1 x2 40 12 2000 184.32 30.72 1 x2 36 12 2211.84 61.44 1 x1 36 12 2211.84 187.5 25 1 x1 90 12 2250 200 25 1 x2 40 10 2000 212.5 26.5625 1 x2 40 10 2125 250 25 1 x2 40 8 2000 300 25 1 x2 48 8 2400 311.04 19.44 1 x2 64 8 2488.32 77.76 1 x1 32 8 2488.32 155.52 2 x1 32 8 2488.32 312.5 25 1 x2 50 8 2500 125 2 x1 40 8 2500 156.25 5 x2 40 8 2500 318.75 26.5625 1 x2 36 6 1912.5 continued on next page.
idt8t49n004anlgi revision a october 15, 2013 5 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs note: each device supports 4 output frequencies (with related input or crystal value) as selected from this table register settings. note: xtal operation: f out =f ref *ps*m/n; clk, nclk input operation: f out =(f ref /p)*ps*m/n. table 3b. i 2 c register map 322.265625 25.78125 2 x1 150 6 1933.59375 375 25 1 x1 90 6 2250 400 25 1 x2 40 5 2000 425 26.5625 1 x2 40 5 2125 491.52 30.72 1 x2 32 4 1966.08 614.4 30.72 1 x2 40 4 2457.6 122.88 2 x1 40 4 2457.6 153.6 5 x2 40 4 2457.6 622.08 19.44 1 x2 64 4 2488.32 625 25 1 x2 50 4 2500 1228.88 30.72 1 x2 40 2 2457.6 output frequencies (mhz) input frequency or crystal frequency (mhz) input clock divider p input clock prescaler ps feedback divider m output divider n vco frequency (mhz) register binary register address register bit d7 d6 d5 d4 d3 d2 d1 d0 0 00000 m0[8] m0[7] m0[6] m0[5] m0[4] m0[3] m0[2] m0[1] 1 00001 m1[8] m1[7] m1[6] m1[5] m1[4] m1[3] m1[2] m1[1] 2 00010 m2[8] m2[7] m2[6] m2[5] m2[4] m2[3] m2[2] m2[1] 3 00011 m3[8] m3[7] m3[6] m3[5] m3[4] m3[3] m3[2] m3[1] 4 00100 unused n0[6] n0[5] n0[4] n0[3] n0[2] n0[1] n0[0] 5 00101 unused n1[6] n1[5] n1[4] n1[3] n1[2] n1[1] n1[0] 6 00110 unused n2[6] n2[5] n2[4] n2[3] n2[2] n2[1] n2[0] 7 00111 unused n3[6] n3[5] n3[4] n3[3] n3[2] n3[1] n3[0] 8 01000 unused bypass0 ps0[1] ps0[0] p0[1] p0[0] cp0[1] cp0[0] 9 01001 unused bypass1 ps1[1] ps1[0] p1[1] p1[0] cp1[1] cp1[0] 10 01010 unused bypass2 ps2[1] ps2[0] p2[1] p2[0] cp2[1] cp2[0] 11 01011 unused bypass3 ps3[1] ps3[0] p3[1] p3[0] cp3[1] cp3[0] 12 01100 reserved lvds_sel0[q3] lvds_sel0[q2] reserved reserved lvds_sel0[q1] lvds_sel0[q0] reserved 13 01101 reserved lvds_sel1[q3] lvds_sel1[q2] reserved reserved lvds_sel1[q1] lvds_sel1[q0] reserved 14 01110 reserved lvds_sel2[q3] lvds_sel2[q2] reserved reserved lvds_sel2[q1] lvds_sel2[q0] reserved 15 01111 reserved lvds_sel3[q3] lvds_sel3[q2] reserved reserved lvds_sel3[q1] lvds_sel3[q0] reserved 16 10000 reserved oe0[q3] oe0[q2] reserved reserved oe0[q1] oe0[q0] reserved 17 10001 reserved oe1[q3] oe1[q2] reserved reserved oe1[q1] oe1[q0] reserved 18 10010 reserved oe2[q3] oe2[q2] reserved reserved oe2[q1] oe2[q0] reserved 19 10011 reserved oe3[q3] oe3[q2] reserved reserved oe3[q1] oe3[q0] reserved 20 10100 reserved reserved reserved reserved reserved reserved unused unused 21 10101 unused unused unused unused unused unused unused unused 22 10110 unused unused unused unused unused unused unused unused 23 10111 unused unused unused unused unused unused unused unused
idt8t49n004anlgi revision a october 15, 2013 6 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 3c. i 2 c function descriptions bits name function pn[1:0] input clock divider register n (n = 0...3) sets the pll input clock divider. the divider value has the range of 1, 2, 4 and 5. see table 3f. pn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. psn(1:0) input prescaler register n (n = 0...3) sets the pll input clock prescaler value. valid prescaler values are x0.5, x1 or x2. see table 3f. set prescaler to x2 for optimum phase noise performance. psn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. mn[8:1] integer feedback divider register n (n = 0...3) sets the integer feedback divider value. based on the femtoclock ng vco range, the applicable feedback dividers settings are 16 thru 250. please note the register value presents bits [8:1] of mn, the lsb of mn is not in the register. mn[8:1] bits are programmed with values to support default configuration settings for fsel[1:0]. nn[6:0] output divider register n (n = 0...3) sets the output divider. the output divider value can range from 2, 3, 4, 5, 6 and 8, 10, 12 to 126 (step: 2). see table 3g for the output divider coding. nn[6:0] bits are programmed with values to support default configuration settings for fsel[1:0]. cpn[1:0] pll bandwidth register n (n = 0...3) sets the femtoclock ng pll bandwidth by controlling the charge pump current. see table 3h. cpn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. bypassn pll bypass register n (n = 0...3) bypasses pll. output of the prescaler is routed through the output divider n to the output fanout buffer. programming a 1 to this bit bypasses the pll. programmin ga0to this bit routes the output of the prescaler through the pll. bypassn bits are programmed with values to support default configuration settings for fsel[1:0]. oen[q0] oen[q1] oen[q2] oen[q3] output enable register n (n = 0...3) sets the outputs to active or high impedance. programmin ga0to this bit sets the outputs to high impedance. programming a 1, sets the outputs to active status. oen[q0], oen[q1], oen[q2], and oen[q3] bits are programmed with values to support default configuration settings for fsel[1:0]. lvds_seln[q0] lvds_seln[q1] lvds_seln[q2] lvds_seln[q3] output style register n (n = 0...3) sets the differential output style to either lvds or lvpecl interface levels. programmin ga1to this bit sets the output styles to lvds levels. programmin ga0to this bit sets the output styles to lvpecl levels. lvds_seln[q0], lvds_seln[q1], lvds_seln[q2], and lvds_seln[q3] bits are programmed with values to support default configuration settings for fsel[1:0].
idt8t49n004anlgi revision a october 15, 2013 7 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 3d. feedback divider mn coding note: mn is always an even value. the mn[0] bits are not implemented. table 3e. input clock divider pn and prescaler psn coding register bit feedback divider mn mn[8:1] do not use 1 thru 15 00001000 16 00001001 18 00001010 20 00001011 22 00001100 thru 00011111 24 thru 62 00100000 64 00100001 66 00100010 68 00100011 70 00100100 72 ... mn 00110010 100 00110011 102 00110100 104 00110101 106 ... mn 01111010 244 01111011 246 01111100 248 01111101 250 clk_sel input p[1:0] ps[1:0] input clock divider p input clock prescaler ps input frequency (mhz) minimum maximum 0xtal xx 00 1 x1 10 40 01 1 x0.5 20 40 1x 1 x2 5 40 1 clk 00 00 1 x1 10 120 01 1 x0.5 20 240 1x 1 x2 5 60 01 00 2 x1 20 240 01 2 x0.5 40 480 1x 2 x2 10 120 10 00 4 x1 40 480 01 4 x0.5 80 800 1x 4 x2 20 240 11 00 5 x1 50 600 01 5 x0.5 100 800 1x 5 x2 25 300
idt8t49n004anlgi revision a october 15, 2013 8 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 3f. output divider nn coding note: x denotes ?don?t care?. table 3g. charge pump cp settings note: femtoclock ng pll stability is only guaranteed over the feedback divider ranges listed is table 3g. register bit output divider n output frequency range n n [6:0] f out_min (mhz) f out_max (mhz) 000000x 2 do not use 0000010 2 955 1250 0000011 3 636.67 833.33 0000100 4 477.5 625 0000101 5 382 500 000011x 6 318.33 416.67 000100x 8 238.75 312.5 000101x 10 191 250 000110x 12 159.1667 208.33 000111x 14 136.4286 178.57 001000x 16 119.375 156.25 ... n (even integer) (1910 n ) (2500 n ) 111101x 124 15.40 20.16 111111x 126 15.16 19.84 register bit feedback divider (m) value range cpn1 cpn0 minimum maximum 0 0 16 48 0 1 48 100 1 0 100 250 1 1 192 250
idt8t49n004anlgi revision a october 15, 2013 9 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs power-up default configuration description the IDT8T49N004I supports a variety of options such as different output styles, number of programmed default frequencies, output en- able and operating temperature range. the device options and de- fault frequencies must be specified at the time of order and are programmed by idt prior to shipment. the document, programma- ble femtoclock ? ng product ordering guide specifies the available order codes, including the device options and default frequency con- figurations. example part number: 8t49n004a-007nlgi, specifies a quad frequency clock generator with default frequencies of 106.25mhz, 133.333mhz, 156.25mhz and 156.25mhz, with 4 lvds outputs that are enabled after power-up, specified over the industrial temperature range and housed in a lead-free (6/6 rohs) vfqfn package. other order codes with respective programmed frequencies are available from idt upon request. after power-up changes to the out- put frequencies are controlled by fsel[1:0] or the i 2 c interface. changes to the style (lvds or lvpecl) and state (active or high im- pedance) of each individual output can also be controlled with the i 2 c interface after power up. table 3h. power-up default settings serial interface configuration description the IDT8T49N004I has an i 2 c-compatible configuration interface to access any of the internal registers (table 3b) for frequency and pll parameter programming. the IDT8T49N004I acts as a slave device on the i 2 c bus and has the address 0b1101110. the interface accepts byte-oriented block write and block read operations. an address byte (p) specifies the register address (table 3b) as the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 3i, 3j). read and write block transfers can be stopped after any complete byte transfer. it is recommended to terminate the i 2 c read or write transfer after accessing byte #23 by sending a stop command. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. table 3i. block write operation table 3j. block read operation fsel1 fsel0 frequency pll state (on or bypass) output state (active or high impedance) output style (lvds or lvpecl) 0 (default) 0 (default) frequency 0 pll state 0 output state 0 output style 0 0 1 frequency 1 pll state 1 output state 1 output style 1 1 0 frequency 2 pll state 2 output state 2 output style 2 1 1 frequency 3 pll state 3 output state 3 output style 3 bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... description start slave address w (0) ack address byte p ack data byte (p) ack data byte (p+1) ack data byte ... ack stop length (bits) 1711818181811 bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... description start slave address w (0) a c k address byte p a c k repeated start slave address r (1) a c k data byte (p) a c k data byte (p+1) a c k data byte ... a c k stop length (bits) 1711811 7118181811
idt8t49n004anlgi revision a october 15, 2013 10 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc =v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc =v cco = 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 3.63v inputs, v i xtal_in other input 0v to 2v -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current outputs, i o (sdata) outputs, i o (lvds) continuous current surge current 50ma 100ma 10ma 10ma 15ma package thermal impedance, ? ja 33.1 ? c/w (0 mps) storage temperature, t stg -65 ? cto150 ? c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.32 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v i cca analog supply current 32 ma i ee power supply current lvpecl 192 ma i cc power supply current lvds 125 ma i cco output supply current lvds 85 ma symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.28 2.5 v cc v v cco output supply voltage 2.375 2.5 2.625 v i cca analog supply current 28 ma i ee power supply current lvpecl 184 ma i cc power supply current lvds 122 ma i cco output supply current lvds 82 ma
idt8t49n004anlgi revision a october 15, 2013 11 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 4c. lvcmos/lvttl dc characteristics, v cc =v cco = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco /2. in the parameter measurement information section, see output load test circuit diagrams. table 4d. differential dc characteristics, v cc =v cco = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: common mode input voltage is at the cross point. table 4e. lvpecl dc characteristics, v cc =v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c note 1: outputs termination with 50 ? to v cco ?2v. symbol parameter test conditions minimum typical maximum units v ih input high voltage sclk, sdata, clk_sel, fsel[1:0] v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage sclk, sdata, clk_sel v cc = 3.3v -0.3 0.8 v sclk, sdata, clk_sel v cc = 2.5v -0.3 0.7 v fsel[1:0] v cc = 3.3v or 2.5v 0.5 v i ih input high current sclk, sdata v cc =v in = 3.465v or 2.625v 5 a clk_sel, fsel[1:0] v cc =v in = 3.465v or 2.625v 150 a i il input low current sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -150 a clk_sel, fsel[1:0] v cc = 3.465v or 2.625v, v in =0v -5 a v oh output high voltage; note 1 lock v cco = 3.465v 2.6 v lock v cco = 2.625v 1.8 v v ol output low voltage; note 1 lock v cco = 3.465v or 2.625v 0.5 v symbol parameter test conditions minimum typical maximum units i ih input high current clk, nclk v cc =v in = 3.465v or 2.625v 150 a i il input low current nclk v cc = 3.465v or 2.625v, v in = 0v -150 a clk v cc = 3.465v or 2.625v, v in =0v -5 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 v ee v cc ? 0.85 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.1 v cco ? 0.75 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v
idt8t49n004anlgi revision a october 15, 2013 12 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 4f. lvpecl dc characteristics, v cc =v cco = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs termination with 50 ? to v cco ?2v. table 4g. lvds dc characteristics, v cc =v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c table 4h. lvds dc characteristics, v cc =v cco = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 5. crystal characteristics symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.2 v cco ? 0.75 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.5 1.0 v symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 345 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.15 1.25 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditions minimum typical maximum units v od differential output voltage 230 340 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.15 1.25 1.375 v ? v os v os magnitude change 50 mv parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz load capacitance (c l )1018pf equivalent series resistance (esr) 50 ?
idt8t49n004anlgi revision a october 15, 2013 13 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs ac electrical characteristics table 6a. pci express jitter specifications, v cc =v cco = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. for additional information, refer to the pci express application note section in the datasheet. note 1: peak-to-peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci express gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 2: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 3: rms jitter after applying system transfer function for the common clock architecture. this specification is based on the pci express base specification revision 0.7, october 2009 and is subject to change pending the final release version of the specification. note 4: this parameter is guaranteed by characterization. not tested in production. symbol parameter test conditions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak; note 1, 4 ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 8.3 13.2 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 0.78 1.35 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.05 0.10 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; note 3, 4 ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.175 0.34 0.8 ps
idt8t49n004anlgi revision a october 15, 2013 14 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs table 6b. ac characteristics, v cc =v cco =3.3v5%or2.5v5%v ee = 0v, t a = -40c to 85 note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: refer to phase noise plots. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoints. note 3: these parameters are guaranteed by characterization. not tested in production. note 4: refer to t lock and t transition in parameter measurement information. symbol parameter test conditions minimum typical maximum units f diff_in differential input frequency 10 312.5 mhz f vco vco frequency 1910 2500 mhz t jit(?) rms phase jitter, random; note 1 25mhz crystal, f out = 100mhz, integration range: 12khz ? 20mhz 258 332 fs 25mhz crystal, f out = 125mhz, integration range: 12khz ? 20mhz 220 291 fs 25mhz crystal, f out = 125mhz, integration range: 10khz ? 1mhz 164 232 fs 25mhz crystal, f out = 156.25mhz, integration range: 12khz ? 20mhz 228 306 fs 25mhz crystal, f out = 156.25mhz, integration range: 10khz ? 1mhz 175 234 fs 25mhz crystal, f out = 250mhz, integration range: 12khz ? 20mhz 212 292 fs 30.72mhz crystal, f out = 491.52mhz, integration range: 12khz ? 20mhz 213 299 fs 19.44mhz crystal, f out = 622.08mhz, integration range: 12khz ? 20mhz 280 386 fs tsk(o) output skew; note 2, 3 lvpecl outputs lvds_sel = 0 45 ps lvds outputs lvds_sel = 1 45 ps t r /t f output rise/fall time lvpecl outputs 20% - 80%, lvds_sel = 0 100 400 ps lvds outputs 20% - 80%, lvds_sel = 1 100 400 ps odc output duty cycle n > 3 output divider; lvds_se l=0or1 47 53 % n ? 3 output divider; lvds_se l=0or1 42 58 % t lock pll lock time; note 3, 4 lock output 20 ms t transition transition time; note 3, 4 lock output 20 ms
idt8t49n004anlgi revision a october 15, 2013 15 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs typical phase noise at 100mhz (3.3v) typical phase noise at 125mhz (3.3v) noise power (dbc/hz) offset frequency (hz) noise power (dbc/hz) offset frequency (hz)
idt8t49n004anlgi revision a october 15, 2013 16 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs typical phase noise at 156.25mhz (3.3v) noise power (dbc/hz) offset frequency (hz)
idt8t49n004anlgi revision a october 15, 2013 17 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs parameter measurement information 3.3v lvpecl output load ac test circuit 3.3v lvds output load ac test circuit differential input levels 2.5v lvpecl output load ac test circuit 2.5v lvds output load ac test circuit rms phase jitter v cc, 2v -1.3v 0.165v 2v v cca v cco 3.3v 5% v cc, v cco v cca v cc v ee nclk clk -0.5v 0.125v v cc, 2v 2v v cca v cco scope qx nqx 2.5v5% power supply +? float gnd v cc, v cco v cca
idt8t49n004anlgi revision a october 15, 2013 18 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs parameter measurement information, continued output skew lvpecl output rise/fall time offset voltage setup output duty cycle/pulse width/period lvds output rise/fall time differential output voltage setup nqx qx nqy qy nq[0:3] q[0:3] nq[0:3] q[0:3] 20% 80% 80% 20% t r t f v od nq[0:3] q[0:3]
idt8t49n004anlgi revision a october 15, 2013 19 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs parameter measurement information, continued locktime & transition time applications information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a1k ? resistor can be used. clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached.
idt8t49n004anlgi revision a october 15, 2013 20 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 =v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels
idt8t49n004anlgi revision a october 15, 2013 21 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpecl driver to xtal input interface
idt8t49n004anlgi revision a october 15, 2013 22 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. clk/nclk input driven by a 3.3v lvpecl driver figure 3c. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl diff e r e nti a l in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo=50 zo=50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo=50 zo=50
idt8t49n004anlgi revision a october 15, 2013 23 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs 2.5v differential clock input interface the clk /nclk accepts lvds, lvpecl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. clk/nclk input driven by a 2.5v lvpecl driver figure 4c. clk/nclk input driven by a 2.5v hcsl driver figure 4b. clk/nclk input driven by a 2.5v lvpecl driver figure 4d. clk/nclk input driven by a 2.5v lvds driver r3 250 ? r4 250 ? r1 6 2. 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
idt8t49n004anlgi revision a october 15, 2013 24 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 )of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5a can be used with either type of output structure. figure 5b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 6a and 6b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 6a. 3.3v lvpecl output termination figure 6b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o =50 ? z o =50 ? lvpecl input 3.3v 3.3v + _
idt8t49n004anlgi revision a october 15, 2013 25 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs termination for 2.5v lvpecl outputs figure 7a and figure 9b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ?2v.forv cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 7b can be eliminated and the termination is shown in figure 7c. figure 7a. 2.5v lvpecl driver termination example figure 7c. 2.5v lvpecl driver termination example figure 7b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
idt8t49n004anlgi revision a october 15, 2013 26 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8t49n004anlgi revision a october 15, 2013 27 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
idt8t49n004anlgi revision a october 15, 2013 28 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs schematic layout figure 9 shows an example of IDT8T49N004I application schematic. the schematic focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. in this example, the device is operated at v cc =v cco =v cca = 3.3v rather than 2.5v. the clk, nclk inputs are provided by a 3.3v lvpecl driver and depicted with a y-termination rather than the standard four resistor vcc-2v thevinin termination for reasons of minimum termination power and layout simplicity. three examples of pecl terminations are shown for the outputs to demonstrate some of the design options available with lvpecl. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the IDT8T49N004I provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the v cc and v cco filters start to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
idt8t49n004anlgi revision a october 15, 2013 29 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs figure 9. IDT8T49N004I application schematic
idt8t49n004anlgi revision a october 15, 2013 30 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs lvpecl power considerations this section provides information on power dissipation and junction temperature for the IDT8T49N004I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N004I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max =v cc_max *i ee_max = 3.465v * 192ma = 665.28mw ? power (outputs) max = 31.55mw/loaded output pair if all outputs are loaded, the total power i s 4 * 31.55mw = 126.2mw total power_ max (3.465v, with all outputs switching) = 665.28w + 126.2mw = 791.48w 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.791w * 33.1c/w = 111.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 32-lead vfqfn, forced convection ? ja by velocity meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
idt8t49n004anlgi revision a october 15, 2013 31 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 12. figure 10. lvpecl driver circuit and termination to calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ?2v. ? for logic high, v out =v oh_max = v cco_max ? 0.75v (v cco_max ?v oh_max )= 0.75v ? for logic low, v out =v ol_max = v cco_max ? 1.6v (v cco_max ?v ol_max )= 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ?(v cco_max ? 2v))/r l ]*(v cco_max ?v oh_max )=[(2v?(v cco_max ?v oh_max ))/r l ]*(v cco_max ?v oh_max )= [(2v ? 0.75v)/50 ? ] * 0.75v = 18.75mw pd_l = [(v ol_max ?(v cco_max ? 2v))/r l ]*(v cco_max ?v ol_max )=[(2v?(v cco_max ?v ol_max ))/r l] *(v cco_max ?v ol_max )= [(2v ? 1.6v)/50 ? ] * 1.6v = 12.80mw total power dissipation per output pair = pd_h + pd_l = 31.55mw v out v cco v cco - 2v q1 rl 50
idt8t49n004anlgi revision a october 15, 2013 32 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs lvds power considerations this section provides information on power dissipation and junction temperature for the IDT8T49N004I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N004I is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v +5% = 3.465v, which gives worst case results. ? power (core) max =v dd_max *(i dd_max +i dda_max ) = 3.465v * (125ma + 32ma) = 544mw ? power (outputs) max =v ddo_max *i ddo_max = 3.465v * 85ma = 294.525mw total power_ max = 544mw + 294.525mw = 876.645mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 8 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.877w * 33.1c/w = 112.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 8. thermal resistance ? ja for 32-lead vfqfn, forced convection ? ja by velocity meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
idt8t49n004anlgi revision a october 15, 2013 33 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs reliability information table 9. ? ja vs. air flow table for a 32-lead vfqfn transistor count the transistor count for IDT8T49N004I is: 26,856 ? ja vs. air flow meters per second 013 multi-layer pcb, jedec standard test boards 33.1c/w 28.1c/w 25.4c/w
idt8t49n004anlgi revision a october 15, 2013 34 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs 32-lead vfqfn package outline and dimensions
idt8t49n004anlgi revision a october 15, 2013 35 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs ordering information table 10. ordering information note: for the specific -ddd order codes, refer to the document programmable femtoclock ? ng product ordering guide . part/order number marking package shipping packaging temperature 8t49n004a-dddnlgi idt8t49n004a-dddnlgi ?lead-free? 32-lead vfqfn tray -40 ? cto85 ? c 8t49n004a-dddnlgi8 idt8t49n004a-dddnlgi ?lead-free? 32-lead vfqfn tape & reel -40 ? cto85 ? c
idt8t49n004anlgi revision a october 15, 2013 36 ?2013 integrated device technology, inc. IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs revision history sheet rev table page description of change date a t10 9, 35 35 changed name of the idt8t49n00xi programmable femtoclock ? ng product ordering information document to programmable femtoclock ? ordering product information deleted quantity from tape & reel, deleted lead free note. 8/20/2013 a t10 1 9 35 changed title to programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs. changed text from ? programmable femtoclock ? ordering product information? to ? programmable femtoclock ? ng product ordering guide?. changed note from ? programmable femtoclock ? ordering product information? to ? programmable femtoclock ? ng product ordering guide?. 9/26/13 a t5 12 changed the min load capacitance from 12pf to 10pf 10/22/13
IDT8T49N004I data sheet programmable femtoclock ? ng lvpecl/lvds clock generator with 4-outputs disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of IDT8T49N004I

	To Download IDT8T49N004I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .